FIG. 1 shows a schematic diagram of a conventional phase generator 10. For example, the phase generator 10 can be a phase digital-to-analog converter (DAC). Generally, the phase generator 10 generates a phase with an analog approach. More specifically, the phase generator 10 interpolates an output clock CLK2 having a novel phase by two differential input clocks (CLK0+, CKL0−, CLK+ and CLK1−) which have different phases. The phase generator 10 comprises a first differential pair transistors M1 and M2, a second differential pair transistors M3 and M4, a first load 12, a second load 14, a first reference current source 16, and a second reference current source 18. Gate ends Na and Nb of the first differential pair transistors M1 and M2 are respectively for receiving a first positive input clock CLK0+ and a first negative input clock CLK0− of the first differential clock. Gate ends Nc and Nd of the second differential pair transistors M3 and M4 are respectively for receiving a second positive input clock CLK1+ and a second negative input clock CLK1− of the second differential clock. The first reference current source 16 and the second reference current source 18 respectively provide a first current I1 and a second current I2 to the first differential pair transistors M1 and M3 and the second differential pair transistors M3 and M4. It is to be noted that, connection relationships between components of the phase generator 10 are shown in FIG. 1, and shall not be described for brevity.
The phase generator 10 interpolates an output clock CLK2 having a novel phase according to a relationship between the first current I1 and the second current I2. FIG. 2 shows a timing sequence of the differential input clocks (CLK0+, CLK0−, CLK1+, CLK1−) and the output clock (CLK2+, CLK2−) generated by the phase generator 10. The first positive input clock CLK0+ and the first negative input clock CLK0− are respectively inputted at the input gate ends Na and Nb at a time point ta, and the second positive input clock CLK1+ and the second negative input clock CLK1− are respectively inputted at the gate ends Nc and Nd at a time point td. Supposing that the first current I1 and the second current I2 are respectively divided into ten equal portions, when a ratio between the first current I1 and the second current I2 is 5:5, a phase of the output clock (CLK2+, CLK2−) is a middle value between that of the first differential input clock (CLK0+, CLK0−) and a second differential input clock (CLK+, CLK1−), i.e., a transition of the output clock (CLK2+, CLK2−) is at a time point tc. When the ratio between the first current I1 and the second current I2 is 9:1, the transition of the output clock (CLK2+, CLK2−) is at a time point tb. In other words, the phase of the output clock (CLK2+, CLK2−) becomes more approximate to that of the first differential input clock (CLK0+, CLK0−) as the first current I1 gets larger. In contrast, the phase of the output clock (CLK2+, CLK2−) becomes more approximate to that of the second differential input clock (CLK1+, CLK1−) as the second current I2 gets larger, and so on. Accordingly, when the first current I1 and the second current I2 are divided into ten equal portions, the phase generator 10 can generate ten different phases between times ta to td according to arrangement of the first current I1 and the second current I2. However, since the phase generator 10 generates different phases with a current steering approach, it is rather power-consuming. Therefore, a solution for solving the power-consuming problem of a phase generator in a mixing signal field is in need.